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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 17:05:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 17:05:47 -0700 |
| commit | 7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85 (patch) | |
| tree | 5fe7f54595de2422651d0d18523dca24984588fb /tests | |
| parent | 6fa6bf483c5e5ba7d3a467c37f66ecf6be9db7d5 (diff) | |
| download | yosys-7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85.tar.gz yosys-7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85.tar.bz2 yosys-7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85.zip | |
Add AREG=2 BREG=2 test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/macc.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index 5dc99ab8e..9d684477f 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -47,7 +47,7 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) ( output signed [SIZEOUT-1:0] accum_out ); // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2; reg rst_reg; reg signed [2*SIZEIN-1:0] mult_reg; reg signed [SIZEOUT-1:0] adder_out, old_result; @@ -56,14 +56,18 @@ always @(posedge clk) begin begin a_reg <= a; b_reg <= b; - mult_reg <= a_reg * b_reg; + a_reg2 <= a_reg; + b_reg2 <= b_reg; + mult_reg <= a_reg2 * b_reg2; rst_reg <= rst; // Store accumulation result into a register adder_out <= adder_out + mult_reg; end if (rst) begin a_reg <= 0; + a_reg2 <= 0; b_reg <= 0; + b_reg2 <= 0; mult_reg <= 0; adder_out <= 0; end |