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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:37:11 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:37:11 -0700 |
commit | c0f26c2da86af6283f6d8380313bd0ad90f1f917 (patch) | |
tree | 6044355d0c421b6539b9a80d0ea271ab382f48e0 /tests | |
parent | 0ebbecf833712165c495fc15fe67b6287cf1fb72 (diff) | |
parent | bdb5e0f29c3e913fb4e701317105363064b9a7d3 (diff) | |
download | yosys-c0f26c2da86af6283f6d8380313bd0ad90f1f917.tar.gz yosys-c0f26c2da86af6283f6d8380313bd0ad90f1f917.tar.bz2 yosys-c0f26c2da86af6283f6d8380313bd0ad90f1f917.zip |
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
Diffstat (limited to 'tests')
-rw-r--r-- | tests/various/peepopt.ys | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 2a660d5c9..886c8cd9d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -78,3 +78,74 @@ clean select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=5 %i +select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D |