iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed bug with memories that do not have a down-to-zero data width	Clifford Wolf	2016-08-22	1	-0/+30
*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+13
*	Bugfix and improvements in memory_share	Clifford Wolf	2016-04-21	1	-0/+21
*	Bugfix in memory_dff	Clifford Wolf	2015-10-31	1	-0/+15
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	1	-2/+2
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-15/+8
*	Added $meminit test case	Clifford Wolf	2015-02-14	1	-0/+30
*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12	1	-0/+11
*	Renamed some of the test cases in tests/simple to avoid name collisions	Clifford Wolf	2014-07-25	1	-9/+9
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	1	-1/+40
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	1	-0/+21
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	1	-0/+20
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+39
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+17
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-0/+41
*	initial import	Clifford Wolf	2013-01-05	1	-0/+19