Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

1 files changed, 39 insertions, 0 deletions

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index eaeee01dd..927ee0438 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -75,3 +75,42 @@ assign y4 = mem2[addr][bit];
 
 endmodule
 
+// ----------------------------------------------------------
+
+module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+
+input clk, wr_enable;
+input [3:0] wr_addr, wr_data, rd_addr;
+output reg [3:0] rd_data;
+
+reg [3:0] memory [0:15];
+
+always @(posedge clk) begin
+	if (wr_enable)
+		memory[wr_addr] <= wr_data;
+	rd_data <= memory[rd_addr];
+end
+
+endmodule
+
+// ----------------------------------------------------------
+
+module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+
+input clk, wr_enable;
+input [3:0] wr_addr, wr_data, rd_addr;
+output [3:0] rd_data;
+
+reg rd_addr_buf;
+reg [3:0] memory [0:15];
+
+always @(posedge clk) begin
+	if (wr_enable)
+		memory[wr_addr] <= wr_data;
+	rd_addr_buf <= rd_addr;
+end
+
+assign rd_data = memory[rd_addr_buf];
+
+endmodule
+