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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-12 10:37:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-12 10:37:47 +0200 |
| commit | cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a (patch) | |
| tree | 7eb6075523bf2a3e09b29467601444b5319f1899 /tests/simple/memory.v | |
| parent | 5215723c64037ba1ee7884423aee1b9c307b5850 (diff) | |
| download | yosys-cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a.tar.gz yosys-cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a.tar.bz2 yosys-cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a.zip | |
Added multi-dim memory test (requires iverilog git head)
Diffstat (limited to 'tests/simple/memory.v')
| -rw-r--r-- | tests/simple/memory.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 9fed1bf3b..db06c56d2 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -194,3 +194,14 @@ always @(posedge clk) begin end endmodule + +// ---------------------------------------------------------- + +module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); + reg [3:0] mem [0:15] [0:15]; + always @(posedge clk) begin + y <= mem[a][b]; + mem[a][b] <= c; + end +endmodule + |