| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 2 | -1/+14 |
| | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | ||||
| * | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 1 | -5/+4 |
| | | | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later. | ||||
| * | tests: Centralize test collection and Makefile generation | Xiretza | 2020-09-21 | 1 | -19/+3 |
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| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -2/+1 |
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| * | anlogic: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-14 | 1 | -12/+14 |
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| * | Simplify breaking tests/arch/*/fsm.ys tests | Eddie Hung | 2020-03-20 | 1 | -4/+1 |
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| * | Call equiv_opt with -multiclock and -assert | Eddie Hung | 2019-12-31 | 1 | -1/+1 |
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| * | Rename memory tests to lutram, add more xilinx tests | Eddie Hung | 2019-12-12 | 1 | -3/+3 |
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| * | Fixed tests | Miodrag Milanovic | 2019-11-11 | 1 | -4/+7 |
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| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 2 | -22/+1 |
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| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 17 | -221/+19 |
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| * | Fix path to yosys | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
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| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 20 | -0/+429 |
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index : iCE40/yosys | |
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