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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 17:44:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 17:44:37 -0800 |
| commit | caab66111e2b5052bd26c8fd64b1324e7e4a4106 (patch) | |
| tree | c6acd63874940ba0ff1176577833cef4bce794a7 /tests/arch/anlogic | |
| parent | 9ab1feeaf11adb6b675ac4034e246cb137d07db9 (diff) | |
| download | yosys-caab66111e2b5052bd26c8fd64b1324e7e4a4106.tar.gz yosys-caab66111e2b5052bd26c8fd64b1324e7e4a4106.tar.bz2 yosys-caab66111e2b5052bd26c8fd64b1324e7e4a4106.zip | |
Rename memory tests to lutram, add more xilinx tests
Diffstat (limited to 'tests/arch/anlogic')
| -rw-r--r-- | tests/arch/anlogic/lutram.ys (renamed from tests/arch/anlogic/memory.ys) | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/lutram.ys index 87b93c2fe..9ebb75443 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic @@ -11,7 +11,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:AL_MAP_LUT2 select -assert-count 8 t:AL_MAP_LUT4 |