| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
| | | * | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 | |
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| | | * | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
| | | * | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
| | | * | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
| | | * | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
| * | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 | |
| * | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 | |
| * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 26 | -343/+629 | |
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| | * | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| | * | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
| * | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 3 | -19/+41 | |
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| | * | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 3 | -6/+6 | |
| | * | | | | | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 2 | -11/+21 | |
| | * | | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 | |
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| * | | | | | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 1 | -15/+5 | |
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| | * \ \ \ \ | Merge pull request #1250 from bwidawsk/master | Eddie Hung | 2019-08-16 | 1 | -15/+5 | |
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| | | * | | | | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 | |
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| * | | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
| * | | | | | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad... | Eddie Hung | 2019-08-12 | 6 | -150/+32 | |
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| * | | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 | |
| * | | | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 5 | -20/+14 | |
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| | * | | | | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 | |
| | * | | | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 2 | -117/+252 | |
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| | * | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 3 | -3/+3 | |
| | * | | | | | Fix spacing | Eddie Hung | 2019-08-06 | 1 | -3/+3 | |
| | * | | | | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -1/+1 | |
| | * | | | | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -14/+8 | |
| * | | | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc | Clifford Wolf | 2019-08-10 | 1 | -8/+36 | |
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| | * | | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+" | Eddie Hung | 2019-08-09 | 1 | -25/+34 | |
| | * | | | | | A bit more on where $lcu comes from | Eddie Hung | 2019-08-09 | 1 | -0/+2 | |
| | * | | | | | Add more comments | Eddie Hung | 2019-08-09 | 1 | -4/+18 | |
| | * | | | | | Add a few comments to document $alu and $lcu | Eddie Hung | 2019-08-08 | 1 | -9/+12 | |
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| * | | | | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -2/+0 | |
| * | | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -10/+17 | |
| * | | | | | Add test | Eddie Hung | 2019-08-07 | 1 | -1/+10 | |
| * | | | | | Remove ice40_unlut | Eddie Hung | 2019-08-07 | 2 | -107/+0 | |
| * | | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 3 | -39/+14 | |
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| * | | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes | David Shah | 2019-08-07 | 1 | -101/+244 | |
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| | * | | | | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 | |
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| * | | | | Merge pull request #1249 from mmicko/anlogic_fix | Clifford Wolf | 2019-08-07 | 1 | -16/+8 | |
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| | * | | | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 | |
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| * / / | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+19 | |
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| * | | Merge pull request #1239 from mmicko/mingw_fix | Clifford Wolf | 2019-08-02 | 3 | -6/+6 | |
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| | * | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 3 | -6/+6 | |
| * | | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 | |
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index : iCE40/yosys | |
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