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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:27:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:29:38 -0700 |
| commit | cc331cf70d9e9f7095e335fc217fd3dbbbe92a93 (patch) | |
| tree | b59eb555c1bf138c7626f1142c072526431f8637 /techlibs | |
| parent | ea8ac8fd7484cc7c3b8929ae339f9aeb49403c36 (diff) | |
| download | yosys-cc331cf70d9e9f7095e335fc217fd3dbbbe92a93.tar.gz yosys-cc331cf70d9e9f7095e335fc217fd3dbbbe92a93.tar.bz2 yosys-cc331cf70d9e9f7095e335fc217fd3dbbbe92a93.zip | |
Add test
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..7e928ec78 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,13 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +delete A:whitebox # Necessary since whiteboxes cannot + # be overwritten... +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |