iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix	Eddie Hung	2019-07-16	8	-29/+120
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\| *	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	7	-8/+8
\| *	ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT	Eddie Hung	2019-07-13	1	-9/+7
\| *	Use Const::from_string() not its constructor...	Eddie Hung	2019-07-12	1	-1/+1
\| *	Off by one	Eddie Hung	2019-07-12	1	-1/+1
\| *	Fix spacing	Eddie Hung	2019-07-12	1	-1/+1
\| *	Remove double push	Eddie Hung	2019-07-12	1	-1/+0
\| *	Map to and from this box if -abc9	Eddie Hung	2019-07-12	1	-2/+3
\| *	ice40_opt to handle this box and opt back to SB_LUT4	Eddie Hung	2019-07-12	1	-0/+48
\| *	Add new box to cells_sim.v	Eddie Hung	2019-07-12	1	-2/+25
\| *	_ABC macro will map and unmap to this new box	Eddie Hung	2019-07-12	2	-0/+34
\| *	Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box	Eddie Hung	2019-07-12	3	-25/+13
* \|	Merge pull request #1183 from whitequark/ice40-always-relut	Clifford Wolf	2019-07-12	1	-11/+5
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\| *	synth_ice40: switch -relut to be always on.	whitequark	2019-07-11	1	-10/+4
\| *	synth_ice40: fix help text typo. NFC.	whitequark	2019-07-11	1	-1/+1
* \|	Merge pull request #1182 from koriakin/xc6s-bram	Eddie Hung	2019-07-11	9	-8/+598
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\| * \|	synth_xilinx: Initial Spartan 6 block RAM inference support.	Marcin Kościelnicki	2019-07-11	9	-8/+598
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* /	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...	Marcin Kościelnicki	2019-07-11	2	-6/+6
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*	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime	Eddie Hung	2019-07-10	3	-6/+15
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\| *	Error out if -abc9 and -retime specified	Eddie Hung	2019-07-10	3	-6/+15
* \|	Merge pull request #1148 from YosysHQ/xc7mux	Eddie Hung	2019-07-10	6	-49/+414
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\| *	Add some spacing	Eddie Hung	2019-07-10	1	-9/+9
\| *	Add some ASCII art explaining mux decomposition	Eddie Hung	2019-07-10	1	-0/+21
\| *	Call muxpack and pmux2shiftx before cmp2lut	Eddie Hung	2019-07-09	1	-9/+12
\| *	Restore opt_clean back to original place	Eddie Hung	2019-07-09	1	-2/+1
\| *	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	Eddie Hung	2019-07-09	1	-0/+2
\| *	Extend using A[1] to preserve don't care	Eddie Hung	2019-07-09	1	-1/+9
\| *	Extend during mux decomposition with 1'bx	Eddie Hung	2019-07-09	1	-24/+3
\| *	Fix typo and comments	Eddie Hung	2019-07-09	1	-4/+4
\| *	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-07-09	2	-19/+28
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\| * \|	synth_xilinx to call commands of synth -coarse directly	Eddie Hung	2019-07-09	1	-3/+20
\| * \|	Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""	Eddie Hung	2019-07-09	1	-2/+2
\| * \|	Fix spacing	Eddie Hung	2019-07-09	1	-1/+1
\| * \|	Fix spacing	Eddie Hung	2019-07-09	1	-1/+1
\| * \|	Decompose mux inputs in delay-orientated (rather than area) fashion	Eddie Hung	2019-07-08	1	-18/+30
\| * \|	Do not call opt -mux_undef (part of -full) before muxcover	Eddie Hung	2019-07-08	1	-1/+5
\| * \|	Add one more comment	Eddie Hung	2019-07-08	1	-0/+3
\| * \|	Less thinking	Eddie Hung	2019-07-08	1	-3/+3
\| * \|	Reword	Eddie Hung	2019-07-08	1	-2/+2
\| * \|	synth_xilinx to call "synth -run coarse" with "-keepdc"	Eddie Hung	2019-07-08	1	-2/+2
\| * \|	Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux	Eddie Hung	2019-07-08	1	-2/+13
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\| * \| \|	Map $__XILINX_SHIFTX in a more balanced manner	Eddie Hung	2019-07-08	1	-36/+49
\| * \| \|	Capitalisation	Eddie Hung	2019-07-08	1	-1/+1
\| * \| \|	Add synth_xilinx -widemux recommended value	Eddie Hung	2019-07-08	1	-1/+1
\| * \| \|	Fixes for 2:1 muxes	Eddie Hung	2019-07-08	2	-5/+30
\| * \| \|	synth_xilinx -widemux=2 is minimum now	Eddie Hung	2019-07-08	1	-4/+7
\| * \| \|	Parametric muxcover costs as per @daveshah1	Eddie Hung	2019-07-08	1	-16/+14
\| * \| \|	atoi -> stoi as per @daveshah1	Eddie Hung	2019-07-08	1	-1/+1
\| * \| \|	Fix $__XILINX_MUXF78 box timing	Eddie Hung	2019-07-01	1	-1/+1
\| * \| \|	Revert "Fix broken MUXFx box, use MUXF7x2 box instead"	Eddie Hung	2019-07-01	3	-37/+36