iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added "check" command	Clifford Wolf	2015-02-13	1	-0/+4
*	Some test related fixes	Clifford Wolf	2015-02-12	1	-4/+4
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04	1	-6/+6
*	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01	1	-1/+1
*	Removed old XST-based xilinx examples	Clifford Wolf	2015-02-01	11	-208/+0
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	9	-1/+84
*	Added missing ports and parameters to xilinx brams	Clifford Wolf	2015-02-01	1	-4/+18
*	Added "make mklibyosys", some minor API changes	Clifford Wolf	2015-02-01	1	-1/+9
*	Added "fsm -encfile"	Clifford Wolf	2015-01-30	1	-2/+9
*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24	1	-2/+2
*	Added $equiv cell type	Clifford Wolf	2015-01-19	1	-1/+23
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	7	-9/+110
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18	3	-468/+55
*	Added synth_xilinx -retime -flatten	Clifford Wolf	2015-01-17	1	-2/+28
*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17	4	-2/+106
*	Added cells.lib	Clifford Wolf	2015-01-16	2	-0/+109
*	Added dff2dffe to synth_xilinx	Clifford Wolf	2015-01-16	1	-0/+2
*	Added more FF types to xilinx/cells.v	Clifford Wolf	2015-01-16	1	-25/+28
*	Fixed xilinx bram clock inverted config	Clifford Wolf	2015-01-16	1	-21/+35
*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16	1	-116/+116
*	Added Xilinx MUXF7 and MUXF8 support	Clifford Wolf	2015-01-15	2	-2/+30
*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13	1	-54/+8
*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08	2	-38/+10
*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08	1	-0/+150
*	More Xilinx bram cleanups	Clifford Wolf	2015-01-07	1	-14/+14
*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07	2	-36/+36
*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06	3	-16/+320
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	3	-24/+65
*	small fix in xilinx/brams.v	Clifford Wolf	2015-01-06	1	-5/+5
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	4	-25/+176
*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06	1	-8/+6
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	2	-13/+41
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	3	-6/+10
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05	7	-19/+172
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04	3	-13/+182
*	Progress in memory_bram	Clifford Wolf	2015-01-03	1	-0/+3
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-1/+1
*	New $mem simlib model	Clifford Wolf	2015-01-02	1	-95/+36
*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-3/+3
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31	1	-0/+20
*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30	1	-0/+2
*	Fixed build with SMALL=1	Clifford Wolf	2014-12-30	1	-0/+2
*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24	1	-49/+5
*	Removed UTF-8 chars from techmap.v	Clifford Wolf	2014-12-12	1	-1/+1
*	Added $dffe cell type	Clifford Wolf	2014-12-08	2	-1/+20
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+32
*	Added "abc" label in synth script	Clifford Wolf	2014-10-31	1	-6/+12
*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31	1	-2/+6
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+6
*	namespace Yosys	Clifford Wolf	2014-09-27	2	-2/+10