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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-04 16:33:59 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-04 16:33:59 +0100 |
| commit | 853e949c0efcf4607fad6d3d4d138f78e1357253 (patch) | |
| tree | 81479ba64e592933cc9d9334ee0967ef6b57acdf /techlibs | |
| parent | a8f4a099b5f1c51ccd46d875c874bbb1e7e5766b (diff) | |
| download | yosys-853e949c0efcf4607fad6d3d4d138f78e1357253.tar.gz yosys-853e949c0efcf4607fad6d3d4d138f78e1357253.tar.bz2 yosys-853e949c0efcf4607fad6d3d4d138f78e1357253.zip | |
Disabled (unused) Xilinx tristate buffers
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index c7f07e400..1f114a22c 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -23,13 +23,13 @@ module BUFG(output O, input I); assign O = I; endmodule -module OBUFT(output O, input I, T); - assign O = T ? 1'bz : I; -endmodule +// module OBUFT(output O, input I, T); +// assign O = T ? 1'bz : I; +// endmodule -module IOBUF(inout IO, output O, input I, T); - assign O = IO, IO = T ? 1'bz : I; -endmodule +// module IOBUF(inout IO, output O, input I, T); +// assign O = IO, IO = T ? 1'bz : I; +// endmodule module INV(output O, input I); assign O = !I; |