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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-03 10:57:01 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-03 10:57:01 +0100 |
| commit | a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 (patch) | |
| tree | 6d6e97eef96e519e273ee7fc34c53acff29f5061 /techlibs | |
| parent | 146f769beef2f6affa9df8e8265e0ca6519d3554 (diff) | |
| download | yosys-a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84.tar.gz yosys-a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84.tar.bz2 yosys-a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84.zip | |
Progress in memory_bram
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 4680e209a..f16bd6bd2 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1540,6 +1540,9 @@ function port_active; endfunction always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin +`ifdef SIMLIB_MEMDELAY + #`SIMLIB_MEMDELAY; +`endif for (i = 0; i < RD_PORTS; i = i+1) begin if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]; |