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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-19 11:55:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-19 11:55:05 +0100 |
| commit | e13a45ae61e05705d9ab6890da60737bd05eb24d (patch) | |
| tree | 07fc6268083538311b2bffe59a105119e55933cd /techlibs | |
| parent | 3a58b8d5b5160b7f31c885d904dbdb752a1c1e62 (diff) | |
| download | yosys-e13a45ae61e05705d9ab6890da60737bd05eb24d.tar.gz yosys-e13a45ae61e05705d9ab6890da60737bd05eb24d.tar.bz2 yosys-e13a45ae61e05705d9ab6890da60737bd05eb24d.zip | |
Added $equiv cell type
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f16bd6bd2..d0feadd81 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1160,12 +1160,34 @@ module \$assert (A, EN); input A, EN; +`ifndef SIMLIB_NOCHECKS always @* begin if (A !== 1'b1 && EN === 1'b1) begin $display("Assertation failed!"); - $finish; + $stop; + end +end +`endif + +endmodule + +// -------------------------------------------------------- + +module \$equiv (A, B, Y); + +input A, B; +output Y; + +assign Y = (A !== 1'bx && A !== B) ? 1'bx : A; + +`ifndef SIMLIB_NOCHECKS +always @* begin + if (A !== 1'bx && A !== B) begin + $display("Equivalence failed!"); + $stop; end end +`endif endmodule |