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* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
* | Fix spacingEddie Hung2019-03-191-1/+1
* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
* | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
* | WorkingEddie Hung2019-03-152-47/+78
* | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
* | MisspellEddie Hung2019-03-141-1/+1
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1433-402/+1656
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| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
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| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| * | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
| * | Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| * | Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| * | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| * | Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| * | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
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| | * | Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | * | Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | * | Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | * | Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | * | Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| * | | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
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| | * | | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
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| * / / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
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| * | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
| * | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
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| | * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
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| * | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
| * | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
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| | * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| | * ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| | * ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
| * | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
| * | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
* | | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
* | | Fix cells_map for SRLEddie Hung2019-03-141-19/+17
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