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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:01:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:01:48 -0700 |
| commit | 8af9979aab5f1434ee7d0e56a85324d78e2fd9f9 (patch) | |
| tree | 0e5da02f25f876ee01e6adb4947bcd5106bdc439 /techlibs | |
| parent | f1a8e8a480a7a88835b02abafd27c03e90de7041 (diff) | |
| download | yosys-8af9979aab5f1434ee7d0e56a85324d78e2fd9f9.tar.gz yosys-8af9979aab5f1434ee7d0e56a85324d78e2fd9f9.tar.bz2 yosys-8af9979aab5f1434ee7d0e56a85324d78e2fd9f9.zip | |
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 169f3b7ce..1978ccf21 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -111,7 +111,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init_msb_first -params -enpol any_or_none\n"); + log(" shregmap -init -params -enpol any_or_none\n"); log(" techmap -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -262,9 +262,8 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none"); + Pass::call(design, "shregmap -initt -params -enpol any_or_none"); Pass::call(design, "techmap -map +/xilinx/ff_map.v"); - Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } |