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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-05 15:16:13 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-05 15:16:13 -0800 |
| commit | 13844c765818b5d8c0d16d62dcc530f688d2c28a (patch) | |
| tree | 64f4ae087a51ba609540a1ac1abf7aa4b71ec0b9 /techlibs | |
| parent | 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 (diff) | |
| download | yosys-13844c765818b5d8c0d16d62dcc530f688d2c28a.tar.gz yosys-13844c765818b5d8c0d16d62dcc530f688d2c28a.tar.bz2 yosys-13844c765818b5d8c0d16d62dcc530f688d2c28a.zip | |
Use "write_edif -pvector bra" for Xilinx EDIF files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c11d885d..3632f348f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -252,7 +252,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "edif")) { if (!edif_file.empty()) - Pass::call(design, stringf("write_edif %s", edif_file.c_str())); + Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str())); } if (check_label(active, run_from, run_to, "blif")) { |