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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:06:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:06:56 -0700 |
| commit | af5706c2a38c010e6c7343aeb1c5d6e26a6b7799 (patch) | |
| tree | c20b50fca67c3835937076cf4d5d3a306a3f5ab9 /techlibs | |
| parent | 8af9979aab5f1434ee7d0e56a85324d78e2fd9f9 (diff) | |
| download | yosys-af5706c2a38c010e6c7343aeb1c5d6e26a6b7799.tar.gz yosys-af5706c2a38c010e6c7343aeb1c5d6e26a6b7799.tar.bz2 yosys-af5706c2a38c010e6c7343aeb1c5d6e26a6b7799.zip | |
Misspell
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1978ccf21..f2c3833a4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -262,7 +262,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "shregmap -initt -params -enpol any_or_none"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "techmap -map +/xilinx/ff_map.v"); Pass::call(design, "opt -fast"); } |