iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	More fine tuning	Eddie Hung	2019-04-11	1	-2/+2
*	Fix cells_map.v	Eddie Hung	2019-04-11	1	-7/+7
*	Fix typo	Eddie Hung	2019-04-11	1	-1/+1
*	Juggle opt calls in synth_xilinx	Eddie Hung	2019-04-11	2	-30/+35
*	WIP for cells_map.v -- maybe working?	Eddie Hung	2019-04-10	1	-32/+27
*	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	Eddie Hung	2019-04-10	1	-31/+38
*	Fix for when B_SIGNED = 1	Eddie Hung	2019-04-10	1	-1/+8
*	Update doc for synth_xilinx	Eddie Hung	2019-04-10	1	-7/+8
*	ff_map.v after abc	Eddie Hung	2019-04-10	1	-5/+5
*	Tidy up	Eddie Hung	2019-04-10	1	-1/+1
*	Move map_cells to before map_luts	Eddie Hung	2019-04-10	1	-11/+12
*	WIP for $shiftx to wide mux	Eddie Hung	2019-04-10	1	-1/+63
*	Update LUT delays	Eddie Hung	2019-04-10	1	-11/+8
*	Add cells.lut to techlibs/xilinx/	Eddie Hung	2019-04-09	2	-0/+16
*	synth_xilinx to call abc with -lut +/xilinx/cells.lut	Eddie Hung	2019-04-09	1	-2/+2
*	Add delays to cells.box	Eddie Hung	2019-04-09	1	-4/+12
*	synth_xilinx with abc9 to use -box	Eddie Hung	2019-04-09	1	-1/+4
*	Add techlibs/xilinx/cells.box	Eddie Hung	2019-04-09	2	-0/+6
*	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	Eddie Hung	2019-04-09	1	-1/+9
*	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	32	-384/+1646
\|\
\| *	xilinx: Add keep attribute where appropriate	David Shah	2019-03-22	2	-25/+31
\| *	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
\| *	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
\| *	Fix typo in ice40_braminit help msg	Clifford Wolf	2019-03-09	1	-1/+1
\| *	Merge pull request #859 from smunaut/ice40_braminit	Clifford Wolf	2019-03-09	4	-37/+212
\| \|\
\| \| *	ice40: Run ice40_braminit pass by default	Sylvain Munaut	2019-03-08	1	-0/+1
\| \| *	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	3	-37/+211
\| * \|	Add link to SF2 / igloo2 macro library guide	Clifford Wolf	2019-03-07	1	-21/+24
\| * \|	Improvements in sf2 cells_sim.v	Clifford Wolf	2019-03-06	2	-30/+251
\| * \|	Add sf2 techmap rules for more FF types	Clifford Wolf	2019-03-06	1	-25/+39
\| * \|	Refactor SF2 iobuf insertion, Add clkint insertion	Clifford Wolf	2019-03-06	3	-83/+152
\| * \|	Improvements in SF2 flow and demo	Clifford Wolf	2019-03-05	2	-8/+23
\| * \|	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
\| \|\ \
\| \| * \|	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| \| * \|	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| \| * \|	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| \| * \|	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| \| * \|	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
\| * \| \|	Merge pull request #850 from daveshah1/ecp5_warn_conflict	Clifford Wolf	2019-03-05	1	-2/+7
\| \|\ \ \
\| \| * \| \|	ecp5: Demote conflicting FF init values to a warning	David Shah	2019-03-04	1	-2/+7
\| \| \|/ /
\| * / /	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
\| \|/ /
\| * \|	Fix ECP5 cells_sim for iverilog	Miodrag Milanovic	2019-03-01	1	-2/+3
\| * \|	Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode	Clifford Wolf	2019-02-28	1	-2/+2
\| \|\ \
\| \| * \|	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	Elms	2019-02-28	1	-2/+2
\| \| \|/
\| * \|	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	6	-19/+19
\| * \|	Merge pull request #794 from daveshah1/ecp5improve	Clifford Wolf	2019-02-28	7	-12/+388
\| \|\ \ \| \| \|/ \| \|/\|
\| \| *	ecp5: Compatibility with Migen AsyncResetSynchronizer	David Shah	2019-02-25	2	-0/+20
\| \| *	ecp5: Add DDRDLLA	David Shah	2019-02-19	1	-0/+9
\| \| *	ecp5: Add DELAYF/DELAYG blackboxes	David Shah	2019-02-19	1	-0/+18
\| \| *	ecp5: Add ECLKSYNCB blackbox	David Shah	2019-02-13	1	-1/+7