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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 11:01:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 11:01:46 -0700 |
| commit | f2042fc7c43af9f43d42fdd2e8034963122ff5eb (patch) | |
| tree | b67fe00c097c53cf63fb06206a987273c38a7430 /techlibs | |
| parent | 2ae26b986cd550e4d3ce4dc5c4f7235144a6f83c (diff) | |
| download | yosys-f2042fc7c43af9f43d42fdd2e8034963122ff5eb.tar.gz yosys-f2042fc7c43af9f43d42fdd2e8034963122ff5eb.tar.bz2 yosys-f2042fc7c43af9f43d42fdd2e8034963122ff5eb.zip | |
synth_xilinx with abc9 to use -box
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 090bcce85..eb37feb83 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -275,7 +275,10 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + if (abc == "abc9") + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + else + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } |