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| | | | * | | | techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| | | | | |/ / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
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| | * | | | | Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-126-150/+32
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
| * | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
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| * | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
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| * | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
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| * | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-126-28/+50
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| * | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
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| * | | | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
| |\ \ \ \ | | | | | | | | | | | | Cleanup a few barnacles across codebase
| | * | | | substr() -> compare()Eddie Hung2019-08-071-3/+3
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| | * | | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
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| | * | | | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| | * | | | | stoi -> atoiEddie Hung2019-08-073-3/+3
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| | * | | | | Fix spacingEddie Hung2019-08-061-3/+3
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| | * | | | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
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| | * | | | | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
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| * | | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
| |\ \ \ \ \ \ | | |_|_|_|_|/ | |/| | | | | Add a few comments to document $alu and $lcu
| | * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| | * | | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| | * | | | | Add more commentsEddie Hung2019-08-091-4/+18
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| | * | | | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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| * | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
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| * | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
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| * | | | | Add testEddie Hung2019-08-071-1/+10
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| * | | | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
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| * | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | | | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
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* | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
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* | | | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-1/+36
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* | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
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* | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* | | | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-087-125/+278
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| * | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-076-123/+277
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| | * | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
| | |\ \ \ \ | | | | | | | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr
| | | * | | | ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | | |/ / / | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
| | |\ \ \ \ | | | |/ / / | | |/| | | anlogic : Fix alu mapping
| | | * | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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| | * / / Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
| | |/ / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
| | |\ \ | | | | | | | | | | Fix formatting for msys2 mingw build
| | | * | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
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* | | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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