Merge remote-tracking branch 'origin/master' into xc7dsp

6 files changed, 50 insertions, 28 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a424d3089..7845a3fed 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,14 +532,26 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant  bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
 module \$lcu (P, G, CI, CO);
 
 parameter WIDTH = 1;
 
-input [WIDTH-1:0] P, G;
-input CI;
+input [WIDTH-1:0] P;    // Propagate
+input [WIDTH-1:0] G;    // Generate
+input CI;               // Carry-in
 
-output reg [WIDTH-1:0] CO;
+output reg [WIDTH-1:0] CO; // Carry-out
 
 integer i;
 always @* begin
@@ -555,6 +567,17 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
 module \$alu (A, B, CI, BI, X, Y, CO);
 
 parameter A_SIGNED = 0;
@@ -563,12 +586,16 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] X, Y;
+input [A_WIDTH-1:0] A;      // Input operand
+input [B_WIDTH-1:0] B;      // Input operand
+output [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,
+                            //          used in combination with
+                            //          reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y;     // Sum
 
-input CI, BI;
-output [Y_WIDTH-1:0] CO;
+input CI;                   // Carry-in (set for $sub)
+input BI;                   // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO;    // Carry-out
 
 wire [Y_WIDTH-1:0] AA, BB;
 
@@ -584,6 +611,7 @@ endgenerate
 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
 
 assign X = AA ^ BB;
+// Full adder
 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
 
 function get_carry;
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 48da0d8ad..de0cbb29d 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
 			dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
+							"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
 				{
 					if (cell->hasPort("\\PRE"))
 						special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
 			pool<SigBit> sig_fed_by_ff;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+							"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					auto output = sigmap(cell->getPort("\\Q")[0]);
 					sig_fed_by_ff.insert(output);
@@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
 			// Look at all the FF inputs
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+							"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					SigBit input;
-					if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+					if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 						input = sigmap(cell->getPort("\\T")[0]);
 					else
 						input = sigmap(cell->getPort("\\D")[0]);
@@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
 						xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
 						xor_cell->setPort("\\OUT", xor_to_ff_wire);
 
-						if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+						if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 							cell->setPort("\\T", xor_to_ff_wire);
 						else
 							cell->setPort("\\D", xor_to_ff_wire);
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 4fa6b0792..1a139ffea 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
 
 			for (int i = 0; i < GetSize(line); i++)
 			{
-				if (in_comment && line.substr(i, 2) == "*/") {
+				if (in_comment && line.compare(i, 2, "*/") == 0) {
 					line[i] = ' ';
 					line[i+1] = ' ';
 					in_comment = false;
 					continue;
 				}
-				if (!in_comment && line.substr(i, 2) == "/*")
+				if (!in_comment && line.compare(i, 2, "/*") == 0)
 					in_comment = true;
 				if (in_comment)
 					line[i] = ' ';
@@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
 				long value;
 
 				token = next_token(line, " \t\r\n");
-				if (token.empty() || token.substr(0, 2) == "//")
+				if (token.empty() || token.compare(0, 2, "//") == 0)
 					break;
 
 				if (token[0] == '@') {
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index e492454fb..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
 				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 02598401c..24668d642 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -183,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
-				min_ce_use = std::stoi(args[++argidx]);
+				min_ce_use = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-nobram") {
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a54b3ac52..265cee6d6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -199,7 +199,7 @@ struct SynthXilinxPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
-				widemux = std::stoi(args[++argidx]);
+				widemux = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-abc9") {