| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | | | * | | | | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 | |
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| | | * | | | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
| | | * | | | | | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad... | Eddie Hung | 2019-08-12 | 6 | -150/+32 | |
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| | * | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 | |
| | * | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
| | * | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
| | * | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 | |
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| * | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 6 | -28/+50 | |
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| | * | | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 | |
| | * | | | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 5 | -20/+14 | |
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| | | * | | | | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 | |
| | | * | | | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
| | | * | | | | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 2 | -117/+252 | |
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| | | * | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 3 | -3/+3 | |
| | | * | | | | | Fix spacing | Eddie Hung | 2019-08-06 | 1 | -3/+3 | |
| | | * | | | | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -1/+1 | |
| | | * | | | | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -14/+8 | |
| | * | | | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc | Clifford Wolf | 2019-08-10 | 1 | -8/+36 | |
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| | | * | | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+" | Eddie Hung | 2019-08-09 | 1 | -25/+34 | |
| | | * | | | | | A bit more on where $lcu comes from | Eddie Hung | 2019-08-09 | 1 | -0/+2 | |
| | | * | | | | | Add more comments | Eddie Hung | 2019-08-09 | 1 | -4/+18 | |
| | | * | | | | | Add a few comments to document $alu and $lcu | Eddie Hung | 2019-08-08 | 1 | -9/+12 | |
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| | * | | | | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -2/+0 | |
| | * | | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -10/+17 | |
| | * | | | | | Add test | Eddie Hung | 2019-08-07 | 1 | -1/+10 | |
| | * | | | | | Remove ice40_unlut | Eddie Hung | 2019-08-07 | 2 | -107/+0 | |
| | * | | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 3 | -39/+14 | |
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| * | | | | | Add wreduce to synth_ice40 -dsp as well | Eddie Hung | 2019-08-09 | 1 | -0/+1 | |
| * | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 | |
| * | | | | | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
| * | | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing | Eddie Hung | 2019-08-08 | 3 | -1/+36 | |
| * | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 | |
| * | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 | |
| * | | | | | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
| * | | | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 | |
| * | | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx | David Shah | 2019-08-08 | 1 | -11/+11 | |
| * | | | | | ecp5: Bring up to date with mul2dsp changes | David Shah | 2019-08-08 | 2 | -2/+10 | |
| * | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | David Shah | 2019-08-08 | 7 | -125/+278 | |
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| | * | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213 | Eddie Hung | 2019-08-07 | 1 | -2/+1 | |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-07 | 6 | -123/+277 | |
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| | | * | | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes | David Shah | 2019-08-07 | 1 | -101/+244 | |
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| | | | * | | | | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 | |
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| | | * | | | | Merge pull request #1249 from mmicko/anlogic_fix | Clifford Wolf | 2019-08-07 | 1 | -16/+8 | |
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| | | | * | | | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 | |
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| | | * / / | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+19 | |
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| | | * | | Merge pull request #1239 from mmicko/mingw_fix | Clifford Wolf | 2019-08-02 | 3 | -6/+6 | |
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| | | | * | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 3 | -6/+6 | |
| * | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 | |
| * | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 | |
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index : iCE40/yosys | |
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