| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 6 | -18/+24 | |
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| | * | | | | | | | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 | |
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| | * | | | | | | | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 | |
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| | | * | | | | | | | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 | |
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| | * | | | | | | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 | |
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| | | * | | | | | | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 | |
| | * | | | | | | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 | |
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| | | * | | | | | | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 | |
| * | | | | | | | | | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 | |
| * | | | | | | | | | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 | |
| * | | | | | | | | | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 | |
| * | | | | | | | | | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 | |
| * | | | | | | | | | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 | |
| * | | | | | | | | | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 | |
| * | | | | | | | | | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 | |
| * | | | | | | | | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 | |
| * | | | | | | | | | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 | |
| * | | | | | | | | | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 | |
| * | | | | | | | | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 2 | -9/+10 | |
| * | | | | | | | | | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 | |
| * | | | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
| * | | | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| * | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 | |
| * | | | | | | | | | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| | * | | | | | | | | | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 15 | -84/+164 | |
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -7/+239 | |
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| | * | | | | | | | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 | |
| | * | | | | | | | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 | |
| | * | | | | | | | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 | |
| | * | | | | | | | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 | |
| | * | | | | | | | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
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| * | | | | | | | | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 | |
| * | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products? | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| * | | | | | | | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 | |
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -33/+18 | |
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| | * | | | | | | | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 | |
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| | | * | | | | | | | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 | |
| | | * | | | | | | | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 | |
| | | * | | | | | | | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 | |
| | | * | | | | | | | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 1 | -28/+10 | |
| | | * | | | | | | | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | | * | | | | | | | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | * | | | | | | | | | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 | |
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| * | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 | |
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 14 | -51/+146 | |
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| | * | | | | | | | | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 | |
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| | | * | | | | | | | | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 | |
| | | * | | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 | |
| | * | | | | | | | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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