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* Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-132-145/+111
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-126-28/+50
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| * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
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| | * substr() -> compare()Eddie Hung2019-08-071-3/+3
| | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
| | * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| | * | stoi -> atoiEddie Hung2019-08-073-3/+3
| | * | Fix spacingEddie Hung2019-08-061-3/+3
| | * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
| | * | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
| * | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
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| | * | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
| | * | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
| | * | | Add more commentsEddie Hung2019-08-091-4/+18
| | * | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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| * | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
| * | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
| * | | Add testEddie Hung2019-08-071-1/+10
| * | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
| * | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
* | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
* | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
* | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-1/+36
* | | Combine techmap callsEddie Hung2019-08-081-2/+1
* | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
* | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
* | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
* | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
* | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-087-125/+278
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| * | | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
| * | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-076-123/+277
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| | * | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
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| | | * | ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
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| | * | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
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| | | * anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
| | * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
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| | * Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
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| | | * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
* | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
* | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
* | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
* | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
* | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
* | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
* | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
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