iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Add '-nosrl' option to synth_xilinx	Eddie Hung	2019-03-21	1	-6/+16
* \|	Fine tune cells_map.v	Eddie Hung	2019-03-20	1	-19/+15
* \|	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-53/+20
* \|	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-11/+67
* \|	Restore original synth_xilinx commands	Eddie Hung	2019-03-19	1	-1/+2
* \|	Fix spacing	Eddie Hung	2019-03-19	1	-1/+1
* \|	Fix INIT for variable length SRs that have been bumped up one	Eddie Hung	2019-03-19	1	-1/+1
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-19	1	-2/+4
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\| *	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	Clifford Wolf	2019-03-19	1	-2/+4
* \|	Only accept <128 for variable length, only if $shiftx exclusive	Eddie Hung	2019-03-16	1	-5/+1
* \|	Cleanup synth_xilinx	Eddie Hung	2019-03-15	2	-3/+2
* \|	Working	Eddie Hung	2019-03-15	2	-47/+78
* \|	Reverse bits in INIT parameter for Xilinx, since MSB is shifted first	Eddie Hung	2019-03-14	1	-16/+32
* \|	Misspell	Eddie Hung	2019-03-14	1	-1/+1
* \|	Revert "Add shregmap -init_msb_first and use in synth_xilinx"	Eddie Hung	2019-03-14	1	-3/+2
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	10	-177/+571
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\| *	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	10	-176/+570
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\| \| *	Revert BRAM WRITE_MODE changes.	Keith Rothman	2019-03-04	1	-12/+12
\| \| *	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| \| *	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| \| *	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| \| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	11	-221/+587
\| * \|	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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* \|	Add shregmap -init_msb_first and use in synth_xilinx	Eddie Hung	2019-03-14	1	-2/+2
* \|	Fix cells_map for SRL	Eddie Hung	2019-03-14	1	-19/+17
* \|	Move shregmap until after first techmap	Eddie Hung	2019-03-13	1	-2/+2
* \|	Refactor $__SHREG__ in cells_map.v	Eddie Hung	2019-03-13	1	-32/+24
* \|	Remove SRL16/32 from cells_xtra	Eddie Hung	2019-02-28	2	-18/+2
* \|	Add SRL16 and SRL32 sim models	Eddie Hung	2019-02-28	1	-0/+39
* \|	Fix SRL16/32 techmap off-by-one	Eddie Hung	2019-02-28	1	-18/+24
* \|	synth_xilinx to call shregmap with enable support	Eddie Hung	2019-02-28	2	-24/+29
* \|	synth_xilinx to use shregmap with -params too	Eddie Hung	2019-02-28	2	-22/+19
* \|	synth_xilinx to now have shregmap call after dff2dffe	Eddie Hung	2019-02-28	1	-0/+2
* \|	Add techmap rule for $__SHREG_DFF_P_ to SRL16/32	Eddie Hung	2019-02-28	1	-0/+71
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*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Add support for Xilinx PS7 block	Eddie Hung	2018-11-10	2	-0/+624
*	xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.	Tim 'mithro' Ansell	2018-10-08	1	-3/+2
*	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-04	2	-2/+14
*	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-03	1	-0/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	2	-3/+36
*	Squelch trailing whitespace, including meta-whitespace	Larry Doolittle	2018-03-11	1	-8/+8
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	4	-23/+30
*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	2	-0/+66
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Added black box modules for all the 7-series design elements (as listed in ug...	Clifford Wolf	2016-03-19	4	-0/+3441
*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	1	-2/+2
*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
*	Added examples/ top-level directory	Clifford Wolf	2015-10-13	7	-77/+0