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* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-071-21/+430
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| * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+3
| * bug fix and cleanupsMiodrag Milanovic2022-02-041-5/+5
| * respect hide_internal flagMiodrag Milanovic2022-02-021-1/+1
| * unify cycles counting and cleanupMiodrag Milanovic2022-02-021-36/+35
| * added stimulus mode and param checkMiodrag Milanovic2022-02-021-5/+31
| * error when no signal foundMiodrag Milanovic2022-01-311-0/+2
| * CleanupMiodrag Milanovic2022-01-311-1/+1
| * Compare bits when not all are definedMiodrag Milanovic2022-01-311-3/+17
| * CleanupMiodrag Milanovic2022-01-311-2/+2
| * message updateMiodrag Milanovic2022-01-311-1/+1
| * Display simulation time dataMiodrag Milanovic2022-01-311-1/+4
| * Use edges when explicitMiodrag Milanovic2022-01-311-1/+5
| * Updating initial state and checksMiodrag Milanovic2022-01-311-15/+28
| * Fix scopeMiodrag Milanovic2022-01-311-1/+1
| * check if stop before startMiodrag Milanovic2022-01-281-0/+3
| * set initial state, only flip-flopsMiodrag Milanovic2022-01-281-1/+28
| * ignore not found private signalsMiodrag Milanovic2022-01-281-0/+3
| * recursive checkMiodrag Milanovic2022-01-281-26/+34
| * Do actual compareMiodrag Milanovic2022-01-281-5/+16
| * Add more options and time handlingMiodrag Milanovic2022-01-281-2/+103
| * Display values of outputsMiodrag Milanovic2022-01-261-12/+10
| * Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
| * Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
| * Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
* | Correct a typo in the manualYRabbit2022-02-021-1/+1
* | Update commentScott Thibault2022-02-021-1/+1
* | Fix unextend method for signed constantsScott Thibault2022-02-021-2/+1
* | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-301-60/+337
* | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-288-3/+239
* | opt_dff: Don't mutate muxes while ModWalker is active.Marcelina Kościelnicka2022-01-281-98/+112
* | memory_bram: Make use of new mem emulation functions to map more RAMs.Marcelina Kościelnicka2022-01-271-18/+10
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* opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
* memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-1/+3
* bugpoint: avoid infinite loop between -connections and -wires.Catherine2021-12-151-1/+1
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-122-1/+212
* opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
* sta: very crude static timing analysis passLofty2021-11-253-30/+341
* show: Fix wire bit indexing.Marcelina Kościelnicka2021-11-121-3/+16
* Merge pull request #3077 from YosysHQ/claire/genlibClaire Xen2021-11-101-21/+40
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| * Spelling fix in abc.ccClaire Xen2021-11-101-1/+1
| * Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
* | iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
* | iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
* | gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
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* Make it work on allMiodrag Milanovic2021-11-051-2/+4
* Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
* flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
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