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| author | Claire Xen <claire@clairexen.net> | 2021-11-10 16:47:54 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-10 16:47:54 +0100 |
| commit | c77d5a2aac406932ba077c20c48f661b3473d626 (patch) | |
| tree | 0ce178059c5d2ffc08ebf4309886e77321d98efb /passes | |
| parent | 093e287a1ef00865be4d0c49dc0a65cc97466d90 (diff) | |
| download | yosys-c77d5a2aac406932ba077c20c48f661b3473d626.tar.gz yosys-c77d5a2aac406932ba077c20c48f661b3473d626.tar.bz2 yosys-c77d5a2aac406932ba077c20c48f661b3473d626.zip | |
Spelling fix in abc.cc
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 9a3e0f170..80c6282c4 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1348,7 +1348,7 @@ struct AbcPass : public Pass { log(" file format).\n"); log("\n"); log(" -genlib <file>\n"); - log(" generate netlists for the specified cell library (using the SIS Genib\n"); + log(" generate netlists for the specified cell library (using the SIS Genlib\n"); log(" file format).\n"); log("\n"); log(" -constr <file>\n"); |