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* Fix muxAB logicEddie Hung2019-07-231-3/+2
* Remove debug printEddie Hung2019-07-231-1/+1
* Simplify and fix for MACsEddie Hung2019-07-232-56/+38
* Fix typoEddie Hung2019-07-231-13/+21
* Fix spacingEddie Hung2019-07-221-2/+2
* Pack hi and lo registers separatelyEddie Hung2019-07-222-39/+70
* Rename according to vendor doc TN1295Eddie Hung2019-07-222-55/+55
* Pack Y registerEddie Hung2019-07-222-22/+38
* Pack adders not just accumulatorsEddie Hung2019-07-222-16/+33
* Restore old ffY behaviourEddie Hung2019-07-191-16/+5
* CleanupEddie Hung2019-07-191-5/+5
* Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-191-4/+4
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| * Do not access beyond boundsEddie Hung2019-07-191-1/+1
| * Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
| * Remove "top" from messageEddie Hung2019-07-191-1/+1
* | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-191-3/+26
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| * Also optimise MSB of $subEddie Hung2019-07-191-3/+3
| * wreduce for $subEddie Hung2019-07-191-0/+23
* | Fine tune ice40_dsp.pmg, add support for packing subsets of registersEddie Hung2019-07-194-35/+47
* | Add support for ice40 signed multipliersEddie Hung2019-07-191-13/+8
* | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-185-106/+179
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| * Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-161-44/+127
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| | * Add commentEddie Hung2019-07-131-0/+5
| | * duplicate -> cloneEddie Hung2019-07-121-3/+3
| | * More cleanupEddie Hung2019-07-121-8/+2
| | * CleanupEddie Hung2019-07-121-29/+51
| | * CleanupEddie Hung2019-07-121-10/+4
| | * CleanupEddie Hung2019-07-121-15/+24
| | * More cleanupEddie Hung2019-07-121-11/+10
| | * CleanupEddie Hung2019-07-121-46/+16
| | * CleanupEddie Hung2019-07-121-7/+1
| | * CleanupEddie Hung2019-07-121-13/+109
| * | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-161-2/+2
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| | * | Do not double count cells in abcEddie Hung2019-07-121-2/+2
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| * | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
| * | Merge pull request #1189 from YosysHQ/eddie/fix1151Clifford Wolf2019-07-151-0/+4
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| | * | Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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| * | Merge pull request #1190 from YosysHQ/eddie/fix_1099Clifford Wolf2019-07-151-4/+8
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| | * | If ConstEval fails do not log_abort() but return gracefullyEddie Hung2019-07-131-4/+8
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| * / opt_lut: make less chatty.whitequark2019-07-131-56/+38
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* | ice40_dsp to accept $__MUL16X16 tooEddie Hung2019-07-181-1/+1
* | Check if RHS is empty firstEddie Hung2019-07-181-0/+2
* | Do not autoremove ffP aor muxPEddie Hung2019-07-181-2/+0
* | Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-182-12/+22
* | Improve A/B reg packingEddie Hung2019-07-182-6/+11
* | Do not autoremove A/B registers since they might have other consumersEddie Hung2019-07-181-2/+0
* | Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
* | Wrong wildcard symbolEddie Hung2019-07-181-1/+1
* | Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-172-5/+11
* | Signed extensionEddie Hung2019-07-162-6/+6