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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 19:33:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 19:33:02 -0700 |
| commit | e9bdc86c0e0ea41d1ee8a610b7f1304c3eaf43e9 (patch) | |
| tree | e1824156cd440b8543cb7fd499a8b1448afa4575 /passes | |
| parent | be0cb7f4b81af91ce47a8baf57d0aff716eecddc (diff) | |
| download | yosys-e9bdc86c0e0ea41d1ee8a610b7f1304c3eaf43e9.tar.gz yosys-e9bdc86c0e0ea41d1ee8a610b7f1304c3eaf43e9.tar.bz2 yosys-e9bdc86c0e0ea41d1ee8a610b7f1304c3eaf43e9.zip | |
duplicate -> clone
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 36f2fafc3..4a6ec3a47 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -761,11 +761,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri auto jt = bit2sinks.find(a_bit); if (jt == bit2sinks.end()) - goto duplicate_lut; + goto clone_lut; for (auto sink_cell : jt->second) if (sink_cell->type != "$lut") - goto duplicate_lut; + goto clone_lut; // Push downstream LUTs past inverter for (auto sink_cell : jt->second) { @@ -787,7 +787,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri sink_cell->setParam("\\LUT", mask); } -duplicate_lut: +clone_lut: driver_mask = driver_lut->getParam("\\LUT"); for (auto &b : driver_mask.bits) { if (b == RTLIL::State::S0) b = RTLIL::State::S1; |