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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 14:52:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 14:52:14 -0700 |
| commit | a37574ccbfe047c09a60bb6ee68b7b5e2ef61337 (patch) | |
| tree | 4c10b8c2677ffb5f6bc2c86ae2b0fcbaadd37f94 /passes | |
| parent | 0dd2a125f655c459b17b5c56c4d34a21d0833bc8 (diff) | |
| download | yosys-a37574ccbfe047c09a60bb6ee68b7b5e2ef61337.tar.gz yosys-a37574ccbfe047c09a60bb6ee68b7b5e2ef61337.tar.bz2 yosys-a37574ccbfe047c09a60bb6ee68b7b5e2ef61337.zip | |
Fix muxAB logic
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 24247d3cf..4b566f0a6 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -187,10 +187,9 @@ code clock clock_pol sigO sigCD sigCD_signed // Loading value into output register is not // supported unless using accumulator - if (muxAB && sigCD != sigO) { - if (muxAB != addAB) + if (muxAB) { + if (sigCD != sigO) reject; - if (muxA) sigCD = port(muxAB, \B); else if (muxB) |