| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 | 2 | -10/+12 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 35 | -709/+709 |
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| * | Added "trace" command | Clifford Wolf | 2014-07-31 | 3 | -2/+100 |
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| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 7 | -9/+11 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 11 | -15/+19 |
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| * | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 3 | -6/+6 |
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| * | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 2 | -14/+43 |
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| * | Added techmap CONSTMAP feature | Clifford Wolf | 2014-07-30 | 1 | -10/+119 |
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| * | Added write_file command | Clifford Wolf | 2014-07-30 | 2 | -0/+77 |
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| * | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 |
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| * | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 2 | -0/+185 |
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| * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 2 | -0/+338 |
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| * | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
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| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 2 | -10/+19 |
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| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 2 | -7/+11 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 25 | -58/+42 |
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| * | Added techmap -extern | Clifford Wolf | 2014-07-27 | 1 | -16/+64 |
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| * | Added topological sorting to techmap | Clifford Wolf | 2014-07-27 | 1 | -20/+52 |
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| * | Added SigPool::check(bit) | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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| * | Fixed bug in opt_clean | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Improved performance of opt_const on large modules | Clifford Wolf | 2014-07-27 | 1 | -29/+54 |
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| * | Fixed a bug in opt_clean and some RTLIL API usage cleanups | Clifford Wolf | 2014-07-27 | 2 | -13/+14 |
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| * | Added log_cmd_error_expection | Clifford Wolf | 2014-07-27 | 1 | -4/+1 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 10 | -87/+85 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 57 | -169/+169 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 46 | -117/+117 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 33 | -138/+138 |
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| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 6 | -74/+29 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 15 | -202/+96 |
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| * | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 3 | -4/+4 |
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| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 6 | -15/+15 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 31 | -101/+147 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 45 | -835/+835 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 45 | -835/+835 |
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| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 2 | -12/+5 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 30 | -465/+171 |
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| * | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 1 | -3/+3 |
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| * | Fixed memory corruption in "opt_reduce" pass | Clifford Wolf | 2014-07-25 | 1 | -5/+7 |
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| * | Disabled cover() for non-linux builds | Clifford Wolf | 2014-07-25 | 1 | -2/+5 |
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| * | Improvements in "cover" command | Clifford Wolf | 2014-07-25 | 1 | -11/+37 |
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| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 6 | -46/+40 |
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| * | Added cover() calls to opt_const | Clifford Wolf | 2014-07-24 | 1 | -9/+45 |
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| * | Added "make SMALL=1" | Clifford Wolf | 2014-07-24 | 1 | -1/+4 |
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| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -6/+6 |
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| * | Added "cover" command | Clifford Wolf | 2014-07-24 | 3 | -1/+117 |
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| * | Various small fixes (from gcc compiler warnings) | Clifford Wolf | 2014-07-23 | 1 | -4/+4 |
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| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 16 | -48/+6 |
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| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 9 | -211/+135 |
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| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 10 | -86/+75 |
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| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 10 | -24/+24 |
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