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* CleanupMiodrag Milanovic2022-01-311-2/+2
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* message updateMiodrag Milanovic2022-01-311-1/+1
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* Display simulation time dataMiodrag Milanovic2022-01-311-1/+4
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* Use edges when explicitMiodrag Milanovic2022-01-311-1/+5
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* Updating initial state and checksMiodrag Milanovic2022-01-311-15/+28
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* Fix scopeMiodrag Milanovic2022-01-311-1/+1
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* check if stop before startMiodrag Milanovic2022-01-281-0/+3
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* set initial state, only flip-flopsMiodrag Milanovic2022-01-281-1/+28
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* ignore not found private signalsMiodrag Milanovic2022-01-281-0/+3
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* recursive checkMiodrag Milanovic2022-01-281-26/+34
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* Do actual compareMiodrag Milanovic2022-01-281-5/+16
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* Add more options and time handlingMiodrag Milanovic2022-01-281-2/+103
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* Display values of outputsMiodrag Milanovic2022-01-261-12/+10
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* Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
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* Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
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* Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
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* opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
| | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
* memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-1/+3
| | | | Fixes #3117.
* bugpoint: avoid infinite loop between -connections and -wires.Catherine2021-12-151-1/+1
| | | | Fixes #3113.
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-122-1/+212
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
| | | | This is a fixed version of #3072.
* sta: very crude static timing analysis passLofty2021-11-253-30/+341
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* show: Fix wire bit indexing.Marcelina Kościelnicka2021-11-121-3/+16
| | | | Fixes #3078.
* Merge pull request #3077 from YosysHQ/claire/genlibClaire Xen2021-11-101-21/+40
|\ | | | | Add genlib support to ABC command
| * Spelling fix in abc.ccClaire Xen2021-11-101-1/+1
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| * Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
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* | iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
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* | gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
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* Make it work on allMiodrag Milanovic2021-11-051-2/+4
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* Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
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* flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
| | | | Fixes #3064.
* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
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* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-1/+7
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-4/+6
| | | | Also fixes some completely broken code in extract_reduce.
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-63/+34
| | | | Fixes #3047.
* dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
| | | | | | This if condition is repeated verbatim, and I can't imagine a legitimate way the inputs could change in between. I imagine it's a copy/paste mistake.
* FfData: some refactoring.Marcelina Kościelnicka2021-10-077-87/+48
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-023-4/+16
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* zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-025-130/+220
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-022-287/+20
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* abc9: make re-entrant (#2993)Eddie Hung2021-09-092-9/+9
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-1/+1
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-6/+22
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| | | | | | | | Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-40/+25
| | | | Fixes #2962.
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