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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 14:23:12 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 15:26:11 +0200 |
commit | faacc7ad897437a8169af9dbbab6818f88c7b1a9 (patch) | |
tree | 8ef1b7953a3cc61aac19172ef680864f0b29b53b /passes | |
parent | 539d4ee90767a839b1c3689dedb6c161b652410f (diff) | |
download | yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.tar.gz yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.tar.bz2 yosys-faacc7ad897437a8169af9dbbab6818f88c7b1a9.zip |
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Fixes #2962.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/proc/proc_prune.cc | 65 |
1 files changed, 25 insertions, 40 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index bd122b91f..9f1080ef6 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -67,51 +67,36 @@ struct PruneWorker } for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) { RTLIL::SigSpec lhs = sigmap(it->first); - bool redundant = true; - for (auto &bit : lhs) { + RTLIL::SigSpec rhs = sigmap(it->second); + SigSpec new_lhs, new_rhs; + SigSpec conn_lhs, conn_rhs; + for (int i = 0; i < GetSize(lhs); i++) { + SigBit bit = lhs[i]; if (bit.wire && !assigned[bit]) { - redundant = false; - break; - } - } - bool remove = false; - if (redundant) { - removed_count++; - remove = true; - } else { - if (root) { - bool promotable = true; - for (auto &bit : lhs) { - if (bit.wire && affected[bit] && !assigned[bit]) { - promotable = false; - break; - } - } - if (promotable) { - RTLIL::SigSpec rhs = sigmap(it->second); - RTLIL::SigSig conn; - for (int i = 0; i < GetSize(lhs); i++) { - RTLIL::SigBit lhs_bit = lhs[i]; - if (lhs_bit.wire && !assigned[lhs_bit]) { - conn.first.append(lhs_bit); - conn.second.append(rhs.extract(i)); - } - } - promoted_count++; - module->connect(conn); - remove = true; + if (!affected[bit] && root) { + conn_lhs.append(bit); + conn_rhs.append(rhs[i]); + } else { + new_lhs.append(bit); + new_rhs.append(rhs[i]); } + assigned.insert(bit); + affected.insert(bit); } - for (auto &bit : lhs) - if (bit.wire) - assigned.insert(bit); - for (auto &bit : lhs) - if (bit.wire) - affected.insert(bit); } - if (remove) + if (GetSize(conn_lhs)) { + promoted_count++; + module->connect(conn_lhs, conn_rhs); + } + if (GetSize(new_lhs) == 0) { + if (GetSize(conn_lhs) == 0) + removed_count++; cs->actions.erase((it++).base() - 1); - else it++; + } else { + it->first = new_lhs; + it->second = new_rhs; + it++; + } } return assigned; } |