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* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-122-1/+212
* opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
* sta: very crude static timing analysis passLofty2021-11-253-30/+341
* show: Fix wire bit indexing.Marcelina Kościelnicka2021-11-121-3/+16
* Merge pull request #3077 from YosysHQ/claire/genlibClaire Xen2021-11-101-21/+40
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| * Spelling fix in abc.ccClaire Xen2021-11-101-1/+1
| * Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
* | iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
* | iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
* | gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
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* Make it work on allMiodrag Milanovic2021-11-051-2/+4
* Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
* flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-1/+7
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-4/+6
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-63/+34
* dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
* FfData: some refactoring.Marcelina Kościelnicka2021-10-077-87/+48
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-023-4/+16
* zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-025-130/+220
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-022-287/+20
* abc9: make re-entrant (#2993)Eddie Hung2021-09-092-9/+9
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-1/+1
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-6/+22
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-40/+25
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-143-0/+110
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-142-10/+41
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-133-2/+114
* Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-131-0/+9
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| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-0/+9
* | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
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* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-111-9/+19
* Add v2 memory cells.Marcelina Kościelnicka2021-08-117-10/+14
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-114-70/+45
* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-093-150/+40
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-081-27/+8
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-291-2/+63
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-23/+30
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-283-2/+3
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