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* Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1626-1135/+1130
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| * Merge pull request #1302 from mmicko/dfflibmap_regressionClifford Wolf2019-08-162-10/+10
| |\ | | | | | | DFFLIBMAP pass regression fix
| | * Regression in abc9Miodrag Milanovic2019-08-161-1/+1
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| | * Just needed IDs to be IdStringMiodrag Milanovic2019-08-161-9/+9
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| * | Add missing NMUX to "abc -g" handlingClifford Wolf2019-08-161-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * ID(\\.*) -> ID(.*)Eddie Hung2019-08-1525-766/+766
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| * Transform all "\\*" identifiers into ID()Eddie Hung2019-08-1525-782/+782
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| * Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-1524-367/+362
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| * More use of IdString::in()Eddie Hung2019-08-153-10/+9
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| * AND with an inverted input, causes X{,N}OR output to be inverted tooEddie Hung2019-08-141-2/+2
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| * Revert "Only sort leaves on non-ANDNOT/ORNOT cells"Eddie Hung2019-08-141-7/+6
| | | | | | | | This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400.
| * Only sort leaves on non-ANDNOT/ORNOT cellsEddie Hung2019-08-141-6/+7
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| * Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"Eddie Hung2019-08-141-4/+8
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| * Since $_ANDNOT_ is not symmetric, do not sort leavesEddie Hung2019-08-121-8/+4
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* | move attributes to wiresMarcin Kościelnicki2019-08-132-28/+9
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* | review fixesMarcin Kościelnicki2019-08-132-29/+4
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* | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-133-20/+356
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-1011-67/+67
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-075-28/+28
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| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-074-16/+16
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| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-22/+20
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| * | stoi -> atoiEddie Hung2019-08-0711-39/+39
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| * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-069-32/+32
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| * | Use State::S{0,1}Eddie Hung2019-08-061-1/+1
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| * | Make liberal use of IdString.in()Eddie Hung2019-08-066-17/+17
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* | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵Clifford Wolf2019-08-091-15/+54
| | | | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add commentEddie Hung2019-08-071-2/+3
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* | | Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
* | | Add TODOEddie Hung2019-08-071-0/+2
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* | | Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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* | Redesign of cell cost APIClifford Wolf2019-08-071-22/+20
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-062-29/+63
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-0/+1
|\ | | | | Visual Studio build fix
| * Visual Studio build fixMiodrag Milanovic2019-07-311-0/+1
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* | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-5/+5
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* Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-161-44/+127
|\ | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
| * Add commentEddie Hung2019-07-131-0/+5
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| * duplicate -> cloneEddie Hung2019-07-121-3/+3
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| * More cleanupEddie Hung2019-07-121-8/+2
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| * CleanupEddie Hung2019-07-121-29/+51
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| * CleanupEddie Hung2019-07-121-10/+4
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| * CleanupEddie Hung2019-07-121-15/+24
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| * More cleanupEddie Hung2019-07-121-11/+10
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| * CleanupEddie Hung2019-07-121-46/+16
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| * CleanupEddie Hung2019-07-121-7/+1
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| * CleanupEddie Hung2019-07-121-13/+109
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* | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-161-2/+2
|\ \ | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * | Do not double count cells in abcEddie Hung2019-07-121-2/+2
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* | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
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* | If ConstEval fails do not log_abort() but return gracefullyEddie Hung2019-07-131-4/+8
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