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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
| commit | 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 (patch) | |
| tree | 900ad3764a73cb81396bcf0c0be1bc92c4df135d /passes/techmap | |
| parent | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (diff) | |
| download | yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.gz yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.bz2 yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.zip | |
Use State::S{0,1}
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 6c70ffd4f..2eaba1b09 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } if (sig.size() == 0) - sig = RTLIL::SigSpec(0, 1); + sig = State::S0; } void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) |