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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 08:22:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 08:22:26 -0700 |
| commit | 7dc15bdd2dff8493ee5786845a5e39427bf3779d (patch) | |
| tree | e0a0c03222b5a177d9ffb79053098f25aabd9bf6 /passes/techmap | |
| parent | 7a912f22b2c3976d72a25ffd605a1cf598b67983 (diff) | |
| download | yosys-7dc15bdd2dff8493ee5786845a5e39427bf3779d.tar.gz yosys-7dc15bdd2dff8493ee5786845a5e39427bf3779d.tar.bz2 yosys-7dc15bdd2dff8493ee5786845a5e39427bf3779d.zip | |
Do not double count cells in abc
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 15e79f9d1..65c7d1bb8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin continue; } } - - cell_stats[RTLIL::unescape_id(c->type)]++; + else + cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; |