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* | | Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-5/+13
* | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...Eddie Hung2019-06-111-15/+10
* | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-111-10/+15
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| * | Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
* | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-101-3/+6
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| * | If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-06-101-3/+6
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| * Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
* | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-4/+4
* | Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"Eddie Hung2019-06-101-26/+6
* | Revert "Refactor to ShregmapTechXilinx7Static"Eddie Hung2019-06-101-86/+46
* | Revert "Add -tech xilinx_static"Eddie Hung2019-06-101-13/+2
* | Revert "Continue support for ShregmapTechXilinx7Static"Eddie Hung2019-06-101-81/+30
* | Revert "shregmap -tech xilinx_static to handle INIT"Eddie Hung2019-06-101-32/+22
* | Fine tune aigerparseEddie Hung2019-06-071-1/+5
* | Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
* | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-061-0/+3
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| * | Move muxpack from passes/techmap to passes/optEddie Hung2019-06-062-257/+0
| * | Update docEddie Hung2019-06-061-4/+5
| * | Add tests, fix for !=Eddie Hung2019-06-061-9/+32
| * | Missing fileEddie Hung2019-06-061-0/+232
| * | Initial adaptation of muxpack from shregmapEddie Hung2019-06-061-0/+1
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| * Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
* | shregmap -tech xilinx_static to handle INITEddie Hung2019-06-051-22/+32
* | Continue support for ShregmapTechXilinx7StaticEddie Hung2019-06-051-30/+81
* | Add -tech xilinx_staticEddie Hung2019-06-051-2/+13
* | Refactor to ShregmapTechXilinx7StaticEddie Hung2019-06-051-46/+86
* | shregmap -tech xilinx_dynamic to work -params and -enpolEddie Hung2019-06-051-6/+26
* | Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-041-4/+4
* | Remove dupeEddie Hung2019-06-031-7/+7
* | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-6/+0
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| * | Move clean from aigerparse to abc9Eddie Hung2019-04-231-0/+1
| * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-221-5/+159
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| | * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-5/+159
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| * | | | Tidy upEddie Hung2019-04-221-6/+0
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* | | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
* | | | Fix spellingEddie Hung2019-05-301-1/+1
* | | | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
* | | | Do not double count LUT1sEddie Hung2019-05-301-1/+0
* | | | Re-enable &dc2Eddie Hung2019-05-301-1/+1
* | | | Reduce -W to 160Eddie Hung2019-05-291-1/+1
* | | | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
* | | | Call &if with -W 250Eddie Hung2019-05-291-1/+6
* | | | Add some debug to abc9Eddie Hung2019-05-291-1/+19
* | | | MisspellEddie Hung2019-05-281-1/+1
* | | | If driver not found, use LUT2Eddie Hung2019-05-271-29/+27
* | | | Disconnect all ABC boxes tooEddie Hung2019-05-271-11/+9
* | | | Parse without wideportsEddie Hung2019-05-271-1/+1
* | | | Remove mapped_mod when doneEddie Hung2019-05-271-0/+2
* | | | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-7/+5
* | | | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-7/+18
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