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Files
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-21
1
-3
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+15
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-21
2
-48
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+114
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Merge pull request #1108 from YosysHQ/clifford/fix1091
Eddie Hung
2019-06-21
1
-45
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+99
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Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
Eddie Hung
2019-06-21
1
-3
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+15
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Actually, there might not be any harm in updating sigmap...
Eddie Hung
2019-06-20
1
-3
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+1
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Add comment as per @cliffordwolf
Eddie Hung
2019-06-20
1
-0
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+11
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Revert "Try way that doesn't involve creating a new wire"
Eddie Hung
2019-06-11
1
-15
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+10
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Do not rename non LUT cells in abc9
Eddie Hung
2019-06-21
1
-11
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+16
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Fix gcc warning of potentially uninitialised
Eddie Hung
2019-06-20
1
-2
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+2
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Fix simple_abc9/generate test with 1'bx at MSB
Eddie Hung
2019-06-20
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-20
2
-3
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+5
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Do not call "setundef -zero" in abc9
Eddie Hung
2019-06-20
1
-5
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+2
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Do not rename non LUT cells in abc9
Eddie Hung
2019-06-21
1
-11
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+16
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Merge remote-tracking branch 'origin/clifford/fix1091' into xc7mux_wip
Eddie Hung
2019-06-21
1
-45
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+99
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Replace "muxcover -freedecode" with "muxcover -dmux=cost"
Clifford Wolf
2019-06-21
1
-15
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+14
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Add "muxcover -freedecode"
Clifford Wolf
2019-06-21
1
-0
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+14
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Improvements in muxcover
Clifford Wolf
2019-06-20
1
-38
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+55
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Add support for partial matches to muxcover, fixes #1091
Clifford Wolf
2019-06-20
1
-7
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+31
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Fix gcc warning of potentially uninitialised
Eddie Hung
2019-06-20
1
-2
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+2
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Fix simple_abc9/generate test with 1'bx at MSB
Eddie Hung
2019-06-20
1
-1
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+1
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Do not call "setundef -zero" in abc9
Eddie Hung
2019-06-20
1
-5
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+2
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-20
2
-3
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+5
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Improve shregmap help message, fixes #1113
Clifford Wolf
2019-06-20
1
-0
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+2
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Fix bug in #1078, add entry to CHANGELOG
Eddie Hung
2019-06-19
1
-3
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+3
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Remove iterator based Module::remove as per @cliffordwolf
Eddie Hung
2019-06-18
1
-7
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+6
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&scorr before &sweep, remove &retime as recommended
Eddie Hung
2019-06-17
1
-1
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+1
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Copy not move parameters/attributes
Eddie Hung
2019-06-17
1
-3
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+4
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Fix leak removing cells during ABC integration; also preserve attr
Eddie Hung
2019-06-17
1
-25
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+26
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Re-enable &dc2
Eddie Hung
2019-06-17
1
-1
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+1
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Cleanup
Eddie Hung
2019-06-16
1
-51
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+7
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Get rid of compiler warnings
Eddie Hung
2019-06-14
1
-5
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+5
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Update abc9 -D doc
Eddie Hung
2019-06-14
1
-1
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+2
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Enable "abc9 -D <num>" for timing-driven synthesis
Eddie Hung
2019-06-14
1
-9
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+9
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Further cleanup based on @daveshah1
Eddie Hung
2019-06-14
1
-10
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+0
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-06-14
1
-0
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+9
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ecp5: Add abc9 option
David Shah
2019-06-14
1
-0
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+9
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Remove extra semicolon
Eddie Hung
2019-06-14
1
-1
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+1
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Rip out all non FPGA stuff from abc9
Eddie Hung
2019-06-12
1
-343
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+111
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Fix spelling
Eddie Hung
2019-06-12
1
-1
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+1
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Be more precise when connecting during ABC9 re-integration
Eddie Hung
2019-06-12
1
-1
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+3
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Remove hacky wideports_split from abc9
Eddie Hung
2019-06-12
1
-52
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+4
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Fix compile errors when #if 1 for debug
Eddie Hung
2019-06-12
1
-7
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+8
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Do not call abc9 if no outputs
Eddie Hung
2019-06-12
1
-54
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+65
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More write_xaiger cleanup
Eddie Hung
2019-06-12
1
-1
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+1
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Consistency
Eddie Hung
2019-06-12
1
-1
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+1
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Merge branch 'xc7mux' into xaig
Eddie Hung
2019-06-12
1
-1
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+1
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Typo: wire delay is -W argument
Eddie Hung
2019-06-12
1
-1
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+1
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Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...
Eddie Hung
2019-06-12
1
-6
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+3
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Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-5
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+13
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Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-13
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+5
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