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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:19:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:19:21 -0700 |
| commit | bf3b8d5e45771a543c2481dee5b1b3a9aba0881e (patch) | |
| tree | 2bf3dc07c07a2dd7d7650b192f2051aaa13661f5 /passes/techmap | |
| parent | 234156c01a4086a69ff9ac9f6ae668d64734d525 (diff) | |
| download | yosys-bf3b8d5e45771a543c2481dee5b1b3a9aba0881e.tar.gz yosys-bf3b8d5e45771a543c2481dee5b1b3a9aba0881e.tar.bz2 yosys-bf3b8d5e45771a543c2481dee5b1b3a9aba0881e.zip | |
Remove mapped_mod when done
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 475508e02..acbab959e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -937,6 +937,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); + + design->remove(mapped_mod); } //else //{ |