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* Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6
* Fix from mergeEddie Hung2019-10-041-1/+1
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-041-2/+12
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| * Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
* | Fix merge issuesEddie Hung2019-10-042-10/+2
* | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-68/+67
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-031-0/+14
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| * Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
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| | * Add -select option to aigmapEddie Hung2019-09-301-6/+40
| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
| * | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | No need to punch ports at allEddie Hung2019-09-301-13/+0
* | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
* | Remove need for $currQ port connectionEddie Hung2019-09-301-0/+8
* | Add commentEddie Hung2019-09-301-0/+1
* | scc call on active module module only, plus cleanupEddie Hung2019-09-301-21/+16
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-1/+1
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| * Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
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| | * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-3/+16
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| * | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-3/+16
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| | * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
* | | Fix "scc" call inside abc9 to consider all wiresEddie Hung2019-09-291-1/+1
* | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-78/+65
* | | Split ABC9 based on clocking only, add "abc_mergeability" attr for enEddie Hung2019-09-271-88/+28
* | | Add -select option to aigmapEddie Hung2019-09-271-6/+40
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2710-397/+841
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| * | Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
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| * Revert abc9.ccEddie Hung2019-09-201-1/+1
| * Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
| * Fix first testcase in #1391Eddie Hung2019-09-202-2/+2
| * Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
| * Added extractinv passMarcin Kościelnicki2019-09-192-0/+124
| * Explicitly order function argumentsEddie Hung2019-09-131-4/+15
| * Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-3/+26
| * techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
| * Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-42/+16
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| | * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-16/+10
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| | * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| | * | | Use a dummy box file if none specifiedEddie Hung2019-08-281-3/+8
| | * | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-174/+5
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| | * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-284-88/+456
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| | * | | | | CleanupEddie Hung2019-08-231-130/+59
| | * | | | | Merge branch 'eddie/fix_techmap' into xaig_arrivalEddie Hung2019-08-201-1/+1
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| | * | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
| * | | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ...Clifford Wolf2019-09-051-8/+24
| * | | | | | | Add flatten handling of pre-existing wires as created by interfaces, fixes #1145Clifford Wolf2019-09-051-8/+20
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| * | | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_cleanEddie Hung2019-08-301-16/+10
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| | * | | | | | Output has priority over input when stitching in abc9Eddie Hung2019-08-291-13/+10
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