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authorEddie Hung <eddie@fpgeh.com>2019-08-20 19:48:16 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-20 19:48:16 -0700
commit57493e328ad69b749619bc692130e28ab5c212ee (patch)
tree4201cfb692fed405dfcac9bc82fb6a8e565b9084 /passes/techmap
parentc26c5563845d81048dea35c4aef5f4678e177b23 (diff)
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techmap -max_iter to apply to each module individually
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/techmap.cc10
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b271c8781..a6c1214a7 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -943,7 +943,8 @@ struct TechmapPass : public Pass {
log(" instead of inlining them.\n");
log("\n");
log(" -max_iter <number>\n");
- log(" only run the specified number of iterations.\n");
+ log(" only run the specified number of iterations for each module.\n");
+ log(" default: unlimited\n");
log("\n");
log(" -recursive\n");
log(" instead of the iterative breadth-first algorithm use a recursive\n");
@@ -1157,15 +1158,16 @@ struct TechmapPass : public Pass {
RTLIL::Module *module = *worker.module_queue.begin();
worker.module_queue.erase(module);
+ int module_max_iter = max_iter;
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
- if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
- did_something = true;
+ if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
+ did_something = true;
if (did_something)
module->check();
- if (max_iter > 0 && --max_iter == 0)
+ if (module_max_iter > 0 && --module_max_iter == 0)
break;
}
}