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* Added non-std verilog assume() statementClifford Wolf2015-02-261-11/+29
* Fixed "sat -initsteps" off-by-one bugClifford Wolf2015-02-221-1/+1
* Added "sat -stepsize" and "sat -tempinduct-step"Clifford Wolf2015-02-211-21/+64
* sat docu changeClifford Wolf2015-02-211-0/+3
* When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.Clifford Wolf2015-02-211-0/+5
* Added "sat -tempinduct-baseonly -tempinduct-inductonly"Clifford Wolf2015-02-211-66/+92
* Fixed basecase init for "sat -tempinduct"Clifford Wolf2015-02-211-1/+6
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-36/+37
* format fixes in "sat -dump_json"Clifford Wolf2015-02-191-18/+17
* Added "sat -dump_json" (WaveJSON format)Clifford Wolf2015-02-191-4/+92
* Improved an error messageClifford Wolf2015-01-281-1/+1
* Added "sat -show-ports"Clifford Wolf2015-01-271-2/+7
* Added log_warning() APIClifford Wolf2014-11-091-2/+2
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-6/+6
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Added "sat -prove-skip"Clifford Wolf2014-08-081-2/+16
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-3/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-5/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-4/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-23/+23
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-23/+23
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-051-4/+24
* Small improvement in SAT log messagesClifford Wolf2014-03-131-3/+3
* Added "sat -dump_cnf"Clifford Wolf2014-02-181-5/+34
* Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-181-31/+31
* Added "sat -initsteps"Clifford Wolf2014-02-181-14/+29
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-171-5/+9
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-171-0/+114
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-061-30/+13
* Added support for sat -show @<sel_name>Clifford Wolf2014-02-061-0/+17
* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-061-4/+34
* Added sat -set-init-zero supportClifford Wolf2014-02-061-2/+22
* Added sat -verify and -falsify support for non-prove casesClifford Wolf2014-02-061-14/+26
* added sat -falsifyClifford Wolf2014-02-041-4/+28
* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-041-2/+27
* Addred sat option -ignore_unknown_cellsClifford Wolf2014-02-031-3/+17
* Added sat -show-inputs and -show-outputsClifford Wolf2014-02-011-1/+24
* Added sat -tempinduc and sat -prove-assertsClifford Wolf2014-01-191-10/+41
* Major rewrite of "freduce" commandClifford Wolf2014-01-021-1/+1
* Added sat -prove-x and -set-def-inputsClifford Wolf2013-12-281-32/+96
* Added sat -set-def/-set-*-undef supportClifford Wolf2013-12-271-5/+66
* Renamed sat -set-undef to -set-any-undefClifford Wolf2013-12-271-20/+20
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