diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-06 17:32:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-06 17:32:51 +0100 |
| commit | d4b0f28881e361f53b61e67c4cb5cd04c196d204 (patch) | |
| tree | 04c1b33420ba175b56beb80da44e660151fba8ab /passes/sat/sat.cc | |
| parent | b1a12c5f371d6417c451b73c558f32e02c794f75 (diff) | |
| download | yosys-d4b0f28881e361f53b61e67c4cb5cd04c196d204.tar.gz yosys-d4b0f28881e361f53b61e67c4cb5cd04c196d204.tar.bz2 yosys-d4b0f28881e361f53b61e67c4cb5cd04c196d204.zip | |
Added support for sat -show @<sel_name>
Diffstat (limited to 'passes/sat/sat.cc')
| -rw-r--r-- | passes/sat/sat.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 2530ed418..378546539 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -733,6 +733,10 @@ struct SatPass : public Pass { log(" show the model for the specified signal. if no -show option is\n"); log(" passed then a set of signals to be shown is automatically selected.\n"); log("\n"); + log(" -show @<sel_name>\n"); + log(" add all wires from the specified selection (see help select) to\n"); + log(" the list of signals to be shown.\n"); + log("\n"); log(" -show-inputs, -show-outputs\n"); log(" add all module input (output) ports to the list of shown signals\n"); log("\n"); @@ -1022,6 +1026,19 @@ struct SatPass : public Pass { sets_def.push_back(it.second->name); } + for (auto &str : shows) { + if (str.empty() || str[0] != '@') + continue; + str = RTLIL::escape_id(str.substr(1)); + if (design->selection_vars.count(str) == 0) + log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str)); + RTLIL::Selection &sel = design->selection_vars.at(str); + str.clear(); + for (auto &it : module->wires) + if (sel.selected_member(module->name, it.first)) + str += (str.empty() ? "" : ",") + it.first; + } + if (show_inputs) { for (auto &it : module->wires) if (it.second->port_input) |