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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/sat/sat.cc | |
parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/sat/sat.cc')
-rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 3e1c72224..dce312065 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1141,7 +1141,7 @@ struct SatPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", |