iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	8	-16/+16
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Add warnings for driver-driver conflicts between FFs (and other cells) and ↵	Clifford Wolf	2017-12-12	1	-2/+3
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*	Add src attribute to extra cells generated by proc_dlatch	Clifford Wolf	2017-09-09	1	-7/+9
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*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-7/+19
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*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	2	-19/+43
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*	Fix all undef-muxes in dlatch input cone	Clifford Wolf	2016-06-02	1	-34/+72
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*	Avoid creating undef-muxes when inferring latches in proc_dlatch	Clifford Wolf	2016-06-01	1	-0/+44
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*	Fixed proc_mux performance bug	Clifford Wolf	2016-04-25	1	-0/+3
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*	Fixed performance bug in proc_dlatch	Clifford Wolf	2016-04-24	1	-2/+61
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*	More flexible handling of initialization values	Clifford Wolf	2016-04-22	1	-7/+22
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	8	-8/+8
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*	Preserve empty $pmux default cases	Clifford Wolf	2016-03-31	1	-2/+2
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*	Improved proc_mux performance for huge always blocks	Clifford Wolf	2015-12-02	1	-36/+153
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*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-1/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	8	-23/+23
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*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09	1	-0/+5
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*	Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.	Clifford Wolf	2015-02-24	1	-2/+4
\| \| \| \|	(original patch by Andrew Becker <andrew.becker@epfl.ch>)
*	Added "proc_dlatch"	Clifford Wolf	2015-02-12	3	-1/+311
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*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-1/+1
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-2/+2
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	2	-2/+2
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*	namespace Yosys	Clifford Wolf	2014-09-27	7	-22/+58
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*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12	2	-2/+3
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-81/+81
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	2	-5/+5
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	4	-11/+8
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	6	-39/+44
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-6/+6
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-12/+3
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-6/+13
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	3	-82/+82
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	3	-82/+82
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-66/+16
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	2	-11/+10
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	2	-6/+0
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-5/+3
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Fixed memory corruption with new SigSpec API in proc_mux	Clifford Wolf	2014-07-22	1	-7/+3
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	5	-82/+82
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	5	-82/+82
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*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-10/+10
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*	Do not create $dffsr cells with no-op resets in proc_dff	Clifford Wolf	2014-06-19	1	-0/+5
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*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21	1	-2/+6
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*	Tiny cleanup in proc_mux.cc	Clifford Wolf	2014-01-03	1	-3/+0
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