diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 22:47:57 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 23:10:58 +0200 |
commit | 6aa792c864444324a1b140c2b63bd860f0cc3914 (patch) | |
tree | 07b2bf3003864337df616a21374c046ddc352c62 /passes/proc | |
parent | 7a608437c65e9646ed229055d61b310e7d93e37e (diff) | |
download | yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.gz yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.bz2 yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.zip |
Replaced more old SigChunk programming patterns
Diffstat (limited to 'passes/proc')
-rw-r--r-- | passes/proc/proc_dff.cc | 2 | ||||
-rw-r--r-- | passes/proc/proc_init.cc | 19 |
2 files changed, 10 insertions, 11 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index a8aba903a..5982fd8e4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -382,7 +382,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks()[0].data, sig, + gen_dff(mod, insig, rstval.as_const(), sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4c9b6bcd2..5976c2162 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -58,16 +58,15 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks().size(); i++) { - if (lhs.chunks()[i].wire == NULL) - continue; - RTLIL::Wire *wire = lhs.chunks()[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); - if (value.size() != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); - log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); - wire->attributes["\\init"] = value.as_const(); - offset += wire->width; + for (auto &lhs_c : lhs.chunks()) { + if (lhs_c.wire != NULL) { + RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width); + if (value.size() != lhs_c.wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value)); + log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value)); + lhs_c.wire->attributes["\\init"] = value.as_const(); + } + offset += lhs_c.width; } } } |