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author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/proc | |
parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) | |
download | yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.gz yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.bz2 yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.zip |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/proc')
-rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b5763508a..6cb560f5c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -168,7 +168,7 @@ restart_proc_arst: rspec.expand(), rval.expand(); for (int i = 0; i < int(rspec.chunks().size()); i++) if (rspec.chunks()[i].wire == NULL) - rval.chunks()[i] = rspec.chunks()[i]; + rval.chunks_rw()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { |