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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-19 12:29:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-19 12:29:29 +0200 |
| commit | 1c85584fe5843a43590de3927fe9bde74a04e72e (patch) | |
| tree | 71704e83df84935200b659a13cf52bea8823e4bf /passes/proc | |
| parent | df76da8fd710394e7ea999e90994483da223f545 (diff) | |
| download | yosys-1c85584fe5843a43590de3927fe9bde74a04e72e.tar.gz yosys-1c85584fe5843a43590de3927fe9bde74a04e72e.tar.bz2 yosys-1c85584fe5843a43590de3927fe9bde74a04e72e.zip | |
Do not create $dffsr cells with no-op resets in proc_dff
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_dff.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 2ec498fb2..c18446512 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -356,6 +356,11 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) rstval.optimize(); sig.optimize(); + if (rstval == sig) { + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + sync_level = NULL; + } + if (sync_always) { if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); |